RapidIO™ Interconnect Specification
The RapidIO™ architecture was developed to address the
need for a high-performance low pin count packet-switched system
level interconnect to be used in a variety of applications as
an open standard. The architecture is targeted toward networking,
telecom, and high performance embedded applications. It is intended
primarily as an intra-system interface, allowing chip-to-chip
and board-to-board communications at Gigabyte per second performance
levels. It provides a rich variety of features including high
data bandwidth, low-latency capability and support for high-performance
I/O devices, as well as providing globally shared memory, message
passing, and software managed programming models. In its simplest
form, the interface can be implemented in a FPGA end point. The
interconnect defines a protocol independent of a physical implementation.
The physical features of an implementation utilizing the interconnect
are defined by the requirements of the implementation, such as
I/O signaling levels, interconnect topology, physical layer protocol,
error detection, and so forth. The architecture is intended and
partitioned to allow adaptation to a multitude of applications.
The following files can be freely downloaded:
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||Acrobat (r) PDF file
This Ecma publication is also approved as ISO/IEC 18372.